SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling

Manufacturer: Springer Availability: Usually ships in 24 hours List Price:$125.00 Our Price:$99.60 Authors: Stuart Sutherland Simon Davidmann Peter Flake P. Moorby Description:

Reviews:

Good book for experienced Verilog designers
(my review is about the 2006 2nd-edition, not the 1st older edition!) In general, I agree with the other reviews. This book is written for an assistance of the originators of Verilog, who can the language of Verilog (and its limitations) very to spout out. Devices of Systemverilog of covers of book the new ones like, enum, struct, interfaces, etc, of the prospect "how to write a better RTL-CODE by using Systemverilog instead of Verilog.' For example, it explains pros/cons it (Systemverilog) of the construction of "interface", against a flat group of declarations of module-port (of Verilog). The originators of assistances of discussion appreciate the RTL-CODING of a higher levle of A (slightly) of abstraction. You do not need a specific bottom (C-with-D. conceive-engineer) to draw benefit from this book; you it need right a good knowledge for conventional Verilog. Because of others indicated, this book is not adapted like reference. The paragraphs run well, but it is hard with the consultation by arbitrary matter of the index. Up to now, no book With cover last-delivers cannot move the official IEEE Systemverilog LRM like better reference. And since the book concentrates on the aspect (synthesizeable) of ' design ' of Systemverilog, it does not cover the devices of language non-synthesizeable (like forced classes, random variables, etc...)


Not useful as a reference
System Verilog is the ASIC HDL of the future, and this is one of the first books specifically addressing its use for Design, as opposed to Assertions or Testbenches. As such, it is an important book. And the authors are certainly Verilog experts.

My main criticism of the book is that it's not so useful as a reference. I pull it off this shelf, flip to the back, and often find the Index lacking. It's only four pages long, which is awfully short for such a long technical textbook.



Good introduction to SystemVerilog for the experienced
As an experienced hardware designer who wants to know what SV is all about, this book was great. It introduced the langauge in a natural way, explained what is synthesisable and is more readable than the LRM. You can also download the book examples from the author's website. This is the audience that this book aimed at and it hits the mark, especially as most designers can get the company to pay the high price of the book.

Downsides: there are some differences from the LRM, as this book was written before the final draft, and despite the book saying the chapter 10 complete design example simulates, it doesn't.


Good Overview but redundant
Here my opinions after having bought and having read the book. - if you are fresh étudiant/plus which wants "learns that" the Verilog system then jump this book. This book supposes that you know well already Verilog. - this book treats only the design. The authors project to go up with more for the checking. - if you have the abundance of the money cash ($130 for the design and $130 for the book of checking) or your rich company pays your books then advance and add this book to your library. If free LRM step then read http://www.eda.org/sv/SystemVerilog_3.1a.pdf - the practice, practical, practise. Just by Verilog of reading anybody became a good engineer of design/verification. (... le)Verilog does not hold will not become standard of IEEE as it is. Thus this book will be superceded by a version which is slightly different in any event.



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